1. Field of the Invention
This disclosure relates to semiconductor devices and more particularly, to a semiconductor device having a load resistor and a method of fabricating the same.
2. Description of the Related Art
In recent years, semiconductor devices such as nonvolatile memory devices have been widely used in electronic products like computers and digital cameras. Nonvolatile memory devices are memory devices that can electrically erase or program data. A memory cell of the nonvolatile memory device typically has a floating gate, which is used as a charge storage layer, and a control gate, which is used to control input and output signals.
The nonvolatile memory device further includes delay circuits, high-voltage stabilizing circuits for writing/erasing, and reference voltage generating circuits to perform various operations. These circuits generally require a resistor device, which has a resistor characteristic. In order to promote efficiency during the fabrication of the chip, the resistor device and the memory cell are formed using very similar processes.
As the integration density of semiconductor devices increase, the design rule must decrease. Thus, a floating gate polysilicon layer for a nonvolatile memory device is typically formed by a self-aligned polysilicon (SAP) process. In the SAP process, when an active region and an isolation layer are formed, a floating gate polysilicon layer is formed on the active region at the same time. The floating gate polysilicon layer is formed only on the active region. As a result, when a resistor device is required on the isolation layer, it is not possible to use the floating gate polysilicon layer as a resistor device. Rather, a control gate polysilicon layer is typically used.
FIG. 1A is a plan diagram illustrating a conventional nonvolatile memory device, FIG. 1B is a sectional diagram taken along the line X-X′ of FIG. 1A, and FIG. 1C is a sectional diagram taken along the line Y-Y′ of FIG. 1A.
Referring to FIGS. 1A, 1B and 1C, a cell region C and a resistor region R are prepared in a semiconductor substrate 100. An isolation layer 130 is disposed in the semiconductor substrate 100 to define an active region A. The isolation layer 130 may be a trench isolation layer. The active region A is disposed across the cell region C. The semiconductor substrate 100 in the resistor region R is covered with the isolation layer 130.
A gate oxide layer 135 is disposed on the active region A. In the cell region C, a floating gate electrode 140, an oxide-nitride-oxide (ONO) layer pattern 145, a control gate electrode 167, and a gate hard mask pattern 170 are sequentially stacked on the semiconductor substrate 100 having the gate oxide layer 135. Meanwhile, a stacked gate structure including the floating gate electrode 140, the ONO layer pattern 145, and the control gate electrode 167 may be formed. Also, the control gate electrode 167 and the gate hard mask pattern 170 constitute word line patterns 171. Gate spacers 172 are disposed on sidewalls of the word line patterns 171 and the floating gate electrode 140. The ONO layer pattern 145, the control gate electrode 167, and the gate hard mask pattern 170 are disposed across the active region A in the cell region C, and the floating gate electrode 140 is disposed in a region where the control gate electrode 167 overlaps the active region A.
The control gate electrode 167 includes a first control gate pattern 150, a second control gate pattern 155a, and a gate conductive layer pattern 165, which are sequentially stacked. The first and second control gate patterns 150 and 155a may be formed of a polysilicon layer. The gate conductive layer pattern 165 may be formed of a metal silicide layer, such as a tungsten silicide layer, a cobalt silicide layer, or a nickel silicide layer.
A load resistor pattern 155b is disposed on the isolation layer 130 in the resistor region R. The load resistor pattern 155b is formed to the same thickness using the same material layer as the second control gate pattern 155a. A planarized interlayer insulating layer 175 is disposed on the semiconductor substrate 100 having the word line pattern 171 and the load resistor pattern 155b. A bit line contact plug 190a is disposed in the cell region C to be in contact with the cell active region A through the planarized interlayer insulating layer 175. A resistor contact plug 190b is disposed in the resistor region R to be in contact with the load resistor pattern 155b through the planarized interlayer insulating layer 175. A spacer nitride layer 185 may be disposed to cover sidewalls of the bit line contact plug 190a and the resistor contact plug 190b. 
The load resistor pattern 155b is formed to the same thickness using the same layer as the second control gate pattern 155a. Conventionally, the second control gate pattern 155a is formed to a thickness of about 500 Å, thus the load resistor pattern 155b is also formed to the same thickness as the second control gate pattern 155a. The bit line contact plug 190a and the resistor contact plug 190b are formed at the same time. In this case, as can be seen in region ‘B1’ of FIG. 1C, the bit line contact plug 190a is formed in the condition that the semiconductor substrate 100 is recessed to a depth of 200 to 300 Å. Accordingly, when the resistor contact plug 190b is formed at the same time as the bit line contact plug 190a, a contact margin becomes insufficient because of a small thickness of the load resistor pattern 155b that is formed of the same layer as the second control gate pattern 155a. 
As a result, as can be seen in region ‘B2’ of FIG. 1B, due to the insufficient contact margin, the contact plug 190b may be formed through the load resistor pattern 155b and come into contact with the isolation layer 130. Accordingly, an electrical contact of the resistor contact plug 190b with the load resistor pattern 155b is formed only through a lateral surface of the resistor contact plug 190b, so that contact resistance increases. Also, when the spacer nitride layer 185 is formed to cover the sidewalls of the contact plugs 190a and 190b to enhance electrical properties of the contact plugs 190a and 190b, the resistor contact plug 190b and the load resistor pattern 155b have no electrical connection, thus resulting in contact failures.
Embodiments of the invention address these and other disadvantages of the related art.